In standard CMOS static RAM bitline and dataline memory read circuitry, the bitline and dataline and their symmetrical complementaries receive a signal indicative of the state of a transistor memory cell. This state information is transferred from the bitline to the dataline through n-channel pass transistors. This state information and its complement are further applied to the inputs of a differential sense amplifier.
This memory scheme is disadvantageously subject to a V.sub.T drop across the bitline, and the sense amplifier is not provided with optimum input voltage levels near the thresholds of the sense amplifier. The standard arrangement is further gain-limited, and it tends substantially to delay a signal passing to the dataline. The speed of signals passing along the signal path is further detrimentally affected by the relatively high capacitance level of the dataline.